The present invention relates to microelectromechanical systems (MEMS) fixed and tunable capacitors, filter devices, variable capacitors for energy harvesting, inertial sensors including accelerometers and gyroscopes, and related fabrication processes.
Large-value tunable and/or variable capacitors with small footprints are needed in a variety of applications, including low-frequency tunable filters and electrostatic energy harvesting devices. For example; energy harvesting variable capacitors require large capacitance variation on the order of 100 pF and greater. Although several designs of small-value micromechanical tunable capacitors have been reported in the literature, low actuation voltage tunable capacitors with large values in small form-factor are yet to be shown. See for example, C. Tsai, et al., “An isolated tunable capacitor with linear capacitance-voltage behavior,” Transducers 2003, Boston, Mass., June 2003, pp. 833-836, and D. McCormick, et al., “Ultra-wide tuning range silicon MEMS capacitors on glass with tera-ohm isolation and low parasitics,” Transducers 2005, Seoul, Korea, June 2005, pp. 1075-1079.
To achieve the highest density capacitors, three-dimensional interdigitated plates with narrow and high aspect-ratio vertical gaps are needed. The present inventors have previously developed a high aspect-ratio polysilicon and single crystal silicon (HARPSS) fabrication technique for the realization of high quality factor (Q) low-voltage one-port capacitors on silicon substrate. This is discussed by F. Ayazi and K. Najafi, in “High aspect-ratio combined poly and single-crystal silicon (HARPSS) MEMS technology,” IEEE Journal of Microelectromechanical Systems, Vol. 9, pp. 288-294, September 2000, and P. Monajemi and F. Ayazi, “A high-Q low-voltage HARPSS tunable capacitor,” IEEE IMS '05, Long Beach, Calif., June 2005, pp. 749-752.
Using this fabrication technique, vertical gaps are defined between polysilicon structures and silicon substrate by depositing thermal oxide (sacrificial oxide) and thus can be scaled to values less than 50 nm and aspect-ratio of more than 200. This is discussed by S. Pourkamali, et al., in “High-Q single crystal silicon HARPSS capacitive beam resonators with self-aligned sub-100-nm transduction gaps,” IEEE Journal of Microelectromechanical Systems, Vol. 12, No. 4, pp. 487-496, August 2003.
This fabrication process is well-suited for fabricating high-value capacitors. However, the conventional HARPSS process does not offer different-size self-aligned narrow gaps between polysilicon and single crystal silicon structures, which is a required feature for high-performance tunable capacitors. For this reason, we have developed a modified version of HARPSS, called the self-aligned HARPSS to implement one-port and two-port tunable capacitors. Using this novel fabrication technique, tunable capacitors of different values are implemented in the bulk of a 70 μm thick silicon on insulator (SOI) substrate and are tuned by 240 percent with a tuning voltage as low as 3.5 V.
Thus, there is a need for improved variable capacitor apparatus for use in energy harvesting circuits, RF integrated circuits, and high-sensitivity micromechanical inertial sensors. There is also a need for improved one-port and two-port tunable capacitors for use in RF integrated circuits. There is also a need for a micro-fabrication method to produce low-voltage tunable capacitors.